Commonly assigned U.S. Pat. No. 3,603,776 entitled "Binary Batch Adder Utilising Threshold Counters" provides a summary of the operation and function of binary logic referred to as encoders and decoders. This generally refers to a binary data processing function in which the binary 1 or binary 0 state of a plurality of signal lines representing binary values 1, 2, 4, etc. are related to the binary 1 or binary 0 state of a particular one of other signals lines. An encoder will receive the binary 1 state of a particular one of several input signal lines and provide a coded binary-weighted output on several signal lines each of which represents a particular binary weight. On the other hand, a decoder receives a coded binary-weighted value on a plurality of input signal lines and energizes a particular one of a number of output signal lines.
There are a number of binary data processing functions in which a requirement exists for responding to coded, binary-weighted signals on a plurality of input lines to provide enabling or disabling signals to a plurality of consecutive ones of a sequence of gates. Such a function is required in parallel, binary shifting, wherein a specified number of bit positions at one end or the other of a binary word are to be enabled or disabled to provide a proper shift operation. Also, other data processing functions require that a field of data within a larger group of data be identified to participate in a particular data processing function.
In prior art data processing operations requiring the above mentioned functions, a coded, binary-weighted value would be applied to a decoder in which the logic would respond to the binary-weighted value to provide energization of a particular one of a plurality of output lines related to the value coded. Further logic, or circuitry, would be required to respond to the particular line energized to ultimately enable the consecutive ones of the gates required to identify a field or bit positions to be enabled or blocked in a shifter.